1. Field of the Invention
The invention relates to a semiconductor device and its manufacturing method, particularly, a semiconductor device with a bonding pad made of a wiring layer including aluminum and its manufacturing method.
2. Description of the Related Art
A bonding pad has been known as an electrode for external connection of an input/output terminal or a power supply terminal of a semiconductor integrated circuit or the like. The bonding pad is formed using an aluminum (Al) wiring, for example, and connected with a lead frame or the like through a bonding wire or the like.
Next, a conventional semiconductor device with the bonding pad made of an aluminum (Al) wiring will be described referring to figures. FIG. 40 is a cross-sectional view showing the conventional semiconductor device and its manufacturing method. This semiconductor device has a multi-layered wiring structure.
A transistor 10T is formed on a semiconductor substrate 10 (to be a semiconductor die) as shown in FIG. 40. That is, a gate insulation film 11 and a gate electrode 12 are formed on the semiconductor substrate 10, and a source 13 and a drain 13 are formed on each side thereof, forming the transistor 10T.
A first interlayer insulation film 14 made of, for example, a silicon oxide film (SiO2) is formed on this semiconductor substrate 10, contact holes are formed by etching or the like, corresponding to the source 13 and the drain 13 of the transistor 10T, and first plugs 15 are embedded therein respectively. Furthermore, a first barrier layer 16 made of titanium (Ti) and titanium nitride (TiN) layered in this order is formed on the first interlayer insulation film 14. A first wiring layer 17 made of aluminum (Al) is deposited on this first barrier layer 16 by, for example, a sputtering method, being formed into a predetermined pattern. The source 13 and the drain 13 of the transistor 10T and the first wiring layer 17 are electrically connected through the first plugs 15 respectively.
Furthermore, a second barrier layer 18 which is the same as the first barrier layer 16 is formed on the first wiring layer 17. These first barrier layer 16, first wiring layer 17, and second barrier layer 18 are formed into a predetermined pattern. Then, a second interlayer insulation film 19 which is the same as the first interlayer insulation film 14 is formed on the second barrier layer 18. A contact hole is formed in the second interlayer insulation film 19 according to needs, and a second plug 20 is embedded therein. The second plug electrically connects the first wiring layer 17 with a second wiring layer 22 which will be described below.
Furthermore, a third barrier layer 21 which is the same as the first barrier layer 16 is formed on the second interlayer insulation film 19, and the second wiring layer 22 made of aluminum (Al) is deposited thereon by, for example, a sputtering method. An antireflection layer 53 made of, for example, titanium nitride (TiN) is formed on the second wiring layer 22. Then, patterning is performed to the third barrier layer 21, the second wiring layer 22, and the antireflection layer 53. In this patterning, reflection of exposure to a photoresist (not shown) used as a mask for the patterning can be prevented by the antireflection layer 53. Thus, the exposure and development of the photoresist can be performed with high precision, and thus the patterning of the second wiring layer 22 can be performed with high precision.
Next, a passivation layer 55 covering the second wiring layer 22 and the antireflection layer 53 is formed. Then, the antireflection layer 53 and the passivation layer 55 are etched so as to form an opening 54 exposing the second wiring layer 22. The second wiring layer 22 exposed in this opening 54 is to be a bonding pad which is to be formed with a bonding wire 56 connecting the second wiring layer 22 with a lead frame (not shown).
The relevant technology is described in Japanese Patent Application Publication No. 2004-158678.
FIGS. 41A and 41B are cross-sectional views showing a step of the process of manufacturing the semiconductor device shown in FIG. 40 or the completed semiconductor device, showing a portion near the uppermost layer. The bonding wire 56 is omitted in FIGS. 41A and 41B.
As shown in FIG. 41A, an end portion of the antireflection layer 53 formed on the second wiring layer 22 is exposed in the opening 54 of the passivation layer 55. When moisture 30 containing impurities, that is, moisture used in the semiconductor manufacturing process or moisture in the air reaches these second wiring layer 22 and antireflection layer 53, a defect portion 22H occurs in the second wiring layer 22 due to its eluted aluminum (Al) component, and an eluted component 22F is deposited on the surface of the exposed second wiring layer 22, as shown in FIG. 41B.
This problem occurs since the moisture 30 containing impurities that adheres to the second wiring layer 22 and the antireflection layer 53 functions as an electrolyte to cause cell reaction between the aluminum (Al) component of the second wiring layer 22 and the titanium (Ti) component of the antireflection layer 53. Since the ionization tendency of titanium (Ti) is lower than the ionization tendency of aluminum (Al) in the cell reaction, aluminum (Al) ions move more than titanium (Ti) ions and thus aluminum is eluted.
As a result, a connection failure occurs between the second wiring layer 22 as the bonding pad and the lead frame (not shown) when a wire is bonded thereto, reducing the yield of the semiconductor device.